SMACD 2026

Clock gating is one of the most efficient techniques for reducing power consumption in digital circuits. It is based on deactivating parts of the clock tree, when no clock is needed. Only flip-flops (FF) that actively change their state are clocked. Conventional tools automatically insert clock gates during the synthesis process, but often rely on heuristics to identify insertion points and control signals. We present a more aggressive approach for hierarchically gating the clock of all FFs, at the expense of additional area used for the gating logic. Using the open-source tool Netlist Carpentry, we translate the circuit into a Python object, insert the clock gates, and convert it back to Verilog. We verify the correctness of this transformation with a Yosys-based logic equivalence check. We demonstrate our approach by applying it to the OpenMSP430. We reduced the FF clock activity to 8 % compared to the non-gated version (with an area overhead of 7 %) and beyond the effect of the included manually placed clock gates (23 % activity) or the Yosys-method (20 % activity).