Patent DE 10 2013 114 046

Electronic delay circuit in CMOS technology for emitting an output signal (OUT/OUTB) delayed in time with respect to an input signal (IN), comprising

• a CMOS thyristor primary switch formed from at least two transistors (M3, M6), whose switching signal (VT) occurring at the switching output is fed to a secondary switch which emits the output signal (OUT/OUTB);
• an integration capacitor (C0) which is connected between a supply voltage (VDD) and a node (VCAP) which connects the gate electrode of one transistor (M6) to the drain electrode of the other transistor (M3) of the primary switch and which can be discharged via a discharging means (M2);
• a switch (M4) which receives the input signal (IN) and is used to switch the discharging means (M2);
• reset elements (M5, M7) for resetting the primary switch (M3, M6) after the output signal has changed; characterised in that an additionally connected component is arranged at the switching output (VT) of the primary switch (M3, M6) as a discharge element (C1; M9) for discharging the sub-threshold current of the primary switch (M3, M6).