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Current Publication

Clock Gate Insertion with a Yosys-based Netlist Modification Tool

Manuel Jirsak1, Adrian Pitterling1, Jonas Lienke1, Georg Gläser1
FPGA Ignite Summer School, , Heidelberg, Germany
1IMMS Institut für Mikroelekronik- und Mechatronik-Systeme gemeinnützige GmbH (IMMS GmbH), Ehrenbergstraße 27, 98693 Ilmenau, Germany

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Project

DI-Meta-X

In the Meta-X project, innovative tools for IC design are being created.


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